Method for driving a plasma display panel

ABSTRACT

The method and apparatus is disclosed for driving a plasma display panel to invert the state of a discharge cell included in the panel. The state of a selected cell is changed by a preparatory inverting pulse which is applied to a selected column (or row) electrode, and then an inverting pulse is applied to a selected row (or column) electrode to invert the state of the changed cell wall voltage. Thus, semi-selection trouble does not take place according to this invention.

United States Patent 11 1 Toba et al.

1 1 Nov. 6, 1973 METHOD FOR DRIVING A PLASMA 3,60l,53l 8/1971 Bitzer178/73 1) DISPLAY PANEL 3,513,327 5/1970 Johnson 3l5/l69 R X Inventors:Teruo Toba, Akashi; Shozo Umeda, Kakogawa, both of Japan Assignee:Fujitsu Limited, Kakogawa, Japan Filed:

Appl. No.1

Mar. 24, 1972 Foreign Application Priority Data Mar. 25, [97! Japan46/l7533 References Cited UNITED STATES PATENTS 2,859,385 11 195sBentley "SIS/169R Primary Examiner-Roy Lake Assistant Examiner-LawrenceJ. Dahl Attorney-Staas, Halsey and Gable [57] ABSTRACT The method andapparatus is disclosed for driving a plasma display panel to invert thestate of a discharge cell included in the panel. The state of a selectedcell is changed by a preparatory inverting pulse which is ap plied to aselected column (or row') electrode, and then an inverting pulse isapplied to a selected row (or column) electrode to invert the state ofthe changed cell wall voltage. Thus, semi-selection trouble does nottake place according to this invention.

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FIGQ [3R Flt-113s METHOD FOR DRIVING A PLASMA DISPLAY PANEL BACKGROUNDOF THE INVENTION 1. Field of the Invention This invention relates to theapparatus and method for driving a plasma display panel, and inparticular, to the apparatus and method of inverting the state of adischarge cell, that is, inverting the state from write to erase andvice versa.

2. Description of the Prior Art A typical plasma display panel of theprior art is composed of a pair of electrodes coated by a dielectriclayer such as glass. The electrodes are opposed to each other, and thespace therebetween is filled with a suitable discharging gas such asneon. Letters or figures are displayed by a discharge spot in thedischarge cell formed between the opposed electrodes, and memoryfunction is carried out by wall charges accumulated in the dielectriclayer. A wall voltage generated by the wall charges depends on asustaining voltage and if the waveform of the applied sustaining voltageis, for instance, symmetric, the wall voltage takes a value between zeroand a level, that is, between the erase state and the write state. Whena non-symmetric sustaining voltage is applied, the wall voltage canassume either of two stable states, positive and negative (it may besaid to take three stable states if the zero level is taken intoaccount).

In the case of applying a symmetric voltage, a pulselike sustainingvoltage Vs is previously applied so that the voltage in the dischargingspace periodically changes its polarity as shown in FIG. 1. If a writingvoltage Vw higher than the firing voltage V, is applied, a dischargespot is produced in the discharge cell, the wall charges are accumulatedin the dielectric layer and the wall voltage V is established as shownby the dotted line. Thus, the potential difference between the nextsustaining voltage V and the wall voltage V approaches a value more thanthe firing voltage V,, and hence a discharge spot is produced again sothat the polarity of the wall voltage V is inverted. Therefore, if oncea writing is done and if the applied sustaining voltage V established ata level lower than the firing voltage V,remains, a discharge spot isproduced every time the polarity of the sustaining voltage V s isinverted, and thus the written information is stored and displayed. Inorder to invert the above-mentioned state, that is, to erase, an erasingvoltage V,,- is applied, whose pulse width is narrow or whose peak valuecan barely cause a discharge. By this erasing voltage V a discharge spotis instantaneously produced in the discharge cell but the wall 'voltageis not produced by the next sustaining voltageso that the display iserased.

The potential difference between such erasing voltage V,,- and the wallvoltage due to the previous sustaining voltage has to exceed the firingvoltage V,. The wall voltage after inversion depends on the pulse width.If the pulse width is narrow, the voltage can be rather high and thevoltage just after the application of the sustaining. voltage isdifferent from the voltage remaining after a lapse of time, the level ofwhich depends on the cell to some extent. Therefore, the range of theheight and width of the pulse of the erasing voltage is very small andhence the inversion from display to erase modes of operation cannot besurely carried out.

The selection of the discharge cell to be energized by inverting itswall voltage, is done by so-called voltage coincidence method whereindriving is done from both electrodes and the desired inverting pulse isapplied only to the electrodes of a single cell when the drivingvoltages come to equal value, and hence the discharge is occasionallymade by a pulse voltage applied to a single electrode (so-calledsemi-select trouble).

In the case of applying a non-symmetric sustaining voltage, thesustaining voltage is composed of waveforms A and B as shown in FIG. 2..The waveform A includes a pulse al of a voltage +V and a pulse a of avoltage V, and the waveform B includes a pulse b of a voltage V,, and apulse h of a voltage +V When the wall voltage is l, a discharge spot SP1is produced by only the voltage of the waveform A, and when the wallvoltage is V a discharge spot SP2 is produced by only the voltage of thewaveform B. If the ratio of the number of the waveforms A to that of thewaveform B is 1:10, the ratio of the brightness of the state 1 of thewall voltage V to that of the state 2 of the wall voltage V is about1:10, and hence a display can be carried out by the state 2. Therefore,a memory function is provided with the state 1 corresponding to a logic0 and the state 2 to a logic 1 for instance.

When the conversion of the states is done, converting pulses CPl, CP2and CP3 of the voltage V,, are applied as shown in FIGS. 3A, B and C.FIG. 3A shows the case of conversion from the state 1 to the state 2,wherein the wall voltage V is converted to the wall voltage V by theconverting pulse CPl as shown by the arrow. FIGS. 38 and 3C show thecase of conversion from the state 2 to the state 1, wherein the wallvoltage V is converted to the wall voltage V by the converting pulsesCP2 and CP3 as shown by the arrow. The purpose of the pulses CPl, CP2and CP3 is the same as the converting pulse V shown in FIG. 1, and thesepulses are applied to the selected cell accoring to the voltagecoincidence method. Accordingly, the possibility of semi-select troubleis high.

BRIEF SUMMARY OF THE INVENTION An object of this invention is to providea sure transition of the state of the discharge cell without semiselecttrouble. 1

Another object of this invention is to enlarge the extent of thetransition of the state of the discharge cell.

In order to accomplish these and other objects, according to thisinvention, the transition of the state is carried out in two steps. Thefirst step, a preparatory converting voltage is applied to the row (orcolumn) electrode of the selected discharge cell to change the polarityof the wall voltage, and second, a converting voltage is applied to thecolumn (or row) electrode to change the state of the selected dischargecell. The potential difference between the converting voltage and thewall voltage changed by the preparatory voltage exceeds the firingvoltage.

BRIEF DESCRIPTION OF THE DRAWINGS This invention will be more fullydescribed in conjunction with the drawings, which include:

FIG. 1 is a graph of the prior art showing the conversion of the voltagestates of a discharge cell upon applying a symmetric sustaining voltage;

FIG. 2 is an explanatory graph of the function upon applying anon-symmetric sustaining voltage;

FIGS. 3A, B and C are graphs showing the voltage states of a dischargecell of the prior art and, in particular, showing the conversion of thestate of a discharge cell upon applying a non-symmetric sustainingvoltage;

FIG. 4 is an explanatory view of the electrodes and discharge cells of aplasma display panel;

FIGS. 5A to E show a series of graphs explaining the conversion of thestate of a discharge cell according to the teachings of this inventionupon applying a symmetric sustaining voltage;

FIG. 6 is a block diagram of a circuitry in accordance with thisinvention for carrying out the function shown in FIG. 5;

FIG. 7 shows the waveforms for explaining the function of the parts ofthe circuitry shown in FIG. 6;

FIGS. 8A to E show a series of graphs as another example of theconversion of the state of a discharge cell according to this inventionupon applying a nonsymmetric sustaining voltage;

FIG. 9 is a block diagram of a circuitry for carrying out the functionshown in FIG. 8;

FIG. 10 shows an example of the gate circuit shown in FIG. 9;

FIG. 11 shows an example of the driver shown in FIG. 9;

FIG. 12 shows an example of the decoder shown in FIG. 9;

FIGS. 13A to S show the waveforms for explaining thefunctions of theparts of the circuitry shown in FIG. 9; and

FIGS. 14A to 1-1 show the waveforms of various nonsymmetric sustainingvoltages.

DETAILED DESCRIPTION OF THE INVENTION FIG. 4 shows schematically aplasma display panel wherein the electrodes X, and Y are selected toconvert the state of a discharge cell A.

In the case of applying a symmetric sustaining voltage, a voltage Vshown in FIG. 5 is applied to the selected electrode X while a voltageVy is applied to the selected electrode Y and hence a voltage V isapplied to the selected discharge cell A. That is, a preparatoryconverting voltage V is applied after the application of the sustainingvoltage V to convert the wall voltage V Next, a converting voltage V isapplied so that the potential difference between V and V exceeds thefiring voltage V,; immediately, the discharge is started, but the wallvoltage V is distinguished because the pulse width of V is too small toproduce the wall voltage. A voltage V B is applied to a semi-selectedcell B on the electrode Y,,. The time when the discharge spot isgenerated, shifts to the time when the preparatory converting voltage Vis applied, the converting voltage V,, is not applied, and hence theconversion of the state does not take place. A voltage V is applied tothe semi-selected discharge cell C on the electrode X and the conversionof the state does not occur in like manner because the convertingvoltage V,, has the same polarity as the previous sustaining voltage VTherefore, semi-select trouble does not appear.

A device for carrying out the above-mentioned driving method is shown inFIG. 6, and its function will be hereinafter explained on referring toFIG. 7. A sustaining voltage V a preparatory converting voltage V, and aconverting voltage V,, are applied to a plasma display panel 1 bydrivers 2 and 3 composed of a group of amplifiers such as transistors orthe like. These drivers 2 and 3 are controlled by the output of gatecircuits 4 and 5 composed of a plurality of AND gates and OR circuits.The logical functions of the gate circuits 3 and 4 are carried out underthe control pulse of a location pulse generator 10 and the output ofaddress registers 6 and 7. The address signals are applied to convertthe state of the selected cell through input terminals 8 and 9.

The location pulse generator 10 includes a counter 12 which counts theclock CL derived from a clock generator 11, the counter 12 being shownas an octal notation counter in FIG. 6. The output signals of thecounter 12 are denoted as (l) to (8); the output (1) is coupled to thegate circuit 4 and the sustaining voltage V is applied to each rowelectrode from the driver 2. The output (6) is applied to the gatecircuit 5 and the sustaining voltage is applied to each column electrodefrom the driver 3.

Address signals are added to the input terminals 8 and 9, and the stateconverting signal, which is an erase-command signal in this example, isapplied to the input terminal 13 to enable an AND gate 14 and to reset aflip-flop 15 by the output (2) of the counter 12. The flip-flop 15 isset by the output (5) and hence the 6 output of the flip-flop 15 takes aform shown as (15) in FIG. 7. The output (15) of the flip-flop 15 iscoupled to the AND gates 16 and 18 and an output signal (16) of the ANDgate 16 is derived from the output signal (3) of the counter 12 to beapplied to the gate circuit 5. The preparatory converting voltage V, isapplied to only selected column electrodes from the AND gate 16 and theoutput of address register 7. The output of the counter 12 is added to awaveform shaping-and-delay circuit 17. This circuit 17 is composed of,for instance, a monostable multi-vibrator and a delay-line, and itsinput pulse is waveform-shaped to a narrow pulse by the monostablemulti-vibrator. Thus, the output signal (18), as shown in FIG. 7, of theAND gate 18 is a pulse output having a width smaller than the outputsignal (4) of the counter 12, and it is delayed from the leading edge ofthe output signal (4). The output signal (18) is added to a gate circuit4 and the output of the address register 6 is also added to the gatecircuit 4 and hence the converting voltage V is applied to only selectedrow electrodes by the driver 2. Thus, one voltage denoted as V M isapplied to selected row electrodes and another voltage denoted as V toselected column electrodes to effect a state conversion or erasure inthe selected cell without semi-select trouble, as shown on reference toFIG. 5. The peak value of the preparatory converting voltage V and theconverting voltage V may be equal to that of the sustaining voltage Vand hence the circuit of the drivers 2 and 3 is simple. After the stateconversion, the output signal (18) of the AND gate 18 is delayed throughthe delay circuit 19 and added to the address registers 6 and 7 so thatthese registers are reset.

In contrast to the above example, the preparatory converting voltage Vmay be applied to the selected row electrodes and the converting voltageto the selected column electrodes. In an alternative method of applyingthe sustaining voltage, one half of it may be applied to the rowelectrodes while another half is applied simultaneously to the columnelectrodes in the opposite polarity. In a still further embodiment, asustaining voltage, which changes periodically its own polarity, may beapplied to either one of the row or column electrodes. In short, thepreparatory converting voltage V is applied to either the row or columnelectrodes, the wall voltage of the discharge cell on the selectedelectrodes is changed, and then the converting voltage V, is applied tothe other selected electrodes so that the state of the selected cell isconverted.

The examples described above relate to the case of applying a symmetricsustaining voltage; the case of a non-symmetric sustaining voltage willbe explained as follows. When a voltage V composed of voltages V and V,,is applied to a selected electrode X and a voltage Vy composed of V2 andV is applied to another selected electrode Y a resultant voltage V A isapplied to a selected cell A as shown in FIG. 8C. Accordingly, the wallvoltage V is changed by the preparatory converting voltage V,,. Thendischarge occurs once by the converting voltage V,, when the potentialdifference between the changed wall voltage and the converting voltageV,, exceeds the firing voltage V). However, the wall voltage reaches thelevel V because the pulse is not sufficiently wide. A voltage V isapplied to the semi-selected cell B on the selected electrode Y,, and adischarge spot is produced by the preparatory converting voltage V,, butthe state is not changed. A voltage V,, is applied to the semi-selectedcell C on the selected electrode X, and the state is not changed becausethe voltage V has the same polarity as the sustaining voltage V,. Thus,the state of the selected cell can be converted without semi-selecttrouble.

Referring to FIG. 9, a circuit for driving the display panel will bedescribed as follows. In a plasma display panel 31, the sustainingvoltage is applied to each electrode from drivers 33 and 35 which arecontrolled by the outputs of the gate circuits 37 and 39. The outputs'of a location pulse generator 40 and decoders 42 and 44 are applied tothe gate circuits 37 and 39, respectively. Input address data signals XDand YD are applied to the decoders 42 and 44 from address registers 46and 48 to be decoded.

The location pulse generator 40 includes a clock generator 51, a counter50, a J-K flip-flop 54, AND gates 56, 57, and 58, OR circuits 62 and 64,a monostable multivibrator 66, and a conversion-demand signal CNG isadded to AND gate 58. The counter 50 is an undecimal counter in thisexample, and its output signalsare denoted as (1) to (11 Output signals(1) and are coupled to the gate circuit 37 through the OR circuit 64,and the output (1) is connected to the driver 33. Output signals (6) and(8) are connected to the gate circuit 39 through the OR circuit 62 andthe output signal (8) is coupled to the driver 35. Gate circuits 37 and39 each comprises illustratively, as shown in FIG. 10, an AND gate 60and an OR circuit 62. In the gate circuit 37, the outputs of the decoder42 and the monostable multivibrator 66 come to the input of the AND gate60; the outputs of the AND gate 64 and the AND gate 60 are coupled tothe inputs of the OR circuit 62, and the output of the OR circuit 62 isconnected to the driver 33. In the gate circuit 39, the output signalsof the decoder 44 and the AND gate 50 are connected to the input of theAND gate 60; the out put signals of the OR circuit 62 and the AND gate60 are both connected to the inputs of the OR circuit 62, and the outputof the OR circuit 62 is added to the driver 35.

An example of the driver 33 (or 35) is shown in FIG. 11, wherein O1 toQ12 are transistors and D1 is adiode. The output signal of a monostablemultivibrator 66 is applied to the base of the transistor 02 and itcontrols the switching of the transistor Q1. The output signal (l), asshown in FIG. 13B, of a counter 50 is coupled to the base of thetransistor O4 to control the switching of the transistor Q3. The outputsignals of the gate circuit 37 are coupled to the bases of thetransistors Q6, Q8, Q10 and Q12, respectively, to control the switchingof the transistors Q5, Q7, Q9 and Q11 and to generate the voltages V Vand V,, at the electrodes X1 to Xn. The driver 33 is generally the sameas the driver 35, but does not include transistors Q1 and O2.

An example of decoders 42 (or 44) is shown in FIG. 12. Any one of theoutput signals: of the NAND gates 70 to 79 comes to zero by the input of1248 codes. Numerals 80 to 83 also denote NAND gates.

Next, referring :to FIGS. 13A, to S, the function of the circuit of FIG.9 will be explained. The clock CL (FIG. 13A) of the clock generator SEis counted by the counter 50, and the signals (1), (3), (5), (6), (8)and (10) are shown in FIGS. 138, C, D, E, F and G, respectively. Theoutput of the OR circuit 64 is shown in FIG. 13H. Output signal VMMV isderived from the output of the monostable multivibrator 66, and is shownin FIG. 13M. The signal VFF is shown in FIG. 13N as the output of theflip-flop FF, signals V and V are the voltages applied (see FIGS. and R)to the row and column electrodes, and signal VA is shown in FIG. 138 asthe voltage applied to the selected cell. Usually, the preparatoryconverting voltage and the converting voltage, the hatched parts of thevoltages V and V are not applied. The voltage V, is applied through thediode D1 shown in FIG. 11, simultaneously with the output (10) of thecounter 50 to the row electrode and with output (6) of the counter Sillto the column electrode. The voltage V H is applied through thetransistor Q3, simultaneously with the output (1) of the counter 50 tothe row electrode and with the output (8) of the counter 50 to thecolumn electrode.

When the conversion-command signal CNG is applied to the AND gate 58,the output signal of the AND gate 58 is applied to the flip-flop 54simultaneously with the output signal (1) of the counter 50, and theflip-flop 54 is set by the next clock CL and reset by the output (6).When the flip-flop 54 is set, the AND gates 56 and 57 are enabled by theoutput of the flip-flop 54 and the output (3) of the counter 50 iscoupled to the gate circuit 39. At this time, the input address data YDis decoded by the decoder 44 and applied to the gate circuit 39, andhence the preparatory converting voltage V of the voltage V is appliedonly to the selected column electrode. The output (5) of the counter 50is connected to the monostable multivibrator 66 from the AND gate 57,converted to a narrow pulse and applied to the gate circuit 37 and thedriver 33. This pulse is applied to the base of the transistor ()2 shownin FIG. 11 and the transistor O2 is turned on, whereby the transistor O1is converted to the on-state and the converting voltage V is applied.

At the same time, the input address data XD is decoded by the decoder 42and coupled to the gate circuit 37, and hence the converting voltage isapplied only to the selected row electrode. Thus, the voltage VA isapplied to the selected cell A. The wall voltage V is changed by thepreparatory converting voltage V, and the potential difference betweenthe converting voltage V and the changed wall voltage exceeds the firingvoltage V, so that the discharge takes place. However, the pulse widthof voltage V, is not wide enough to establish the wall voltage and hencethe wall voltage is converted to the level V Converting the semiselectedcell, the semi-select trouble does not take place as described inreference to the graphs of FIG. 8. The above example is the case whenthe state 1 of the wall voltage V is converted to the state 2 of thewall voltage V and the conversion from the state 2 to the state 1 can bedone in a similar way. The method shown in FIG. 3C can be combined withthe method mentioned just above. The preparatory converting voltage Vand the converting voltage V may be added to either column or rowelectrode as well as in the case of the above-mentioned symmetricsustaining voltage.

FIGS. 14A to H show the various methods of applying the sustainingvoltage. In FIGS. 14A and B, two types of voltages, i.e., half of V andhalf of V, are applied to the column and row electrodes at the same timeand in the opposite polarities. The nonsymmetric sustaining voltagecombine with V H and V, and are applied to the discharge cell. Thepreparatory converting voltage and the converting voltage are applied inthe same way as in the above-described example. FIGS. 14C and D show acase wherein the voltages V and V,, are applied to the row and columnelectrodes, respectively. FIGS. 14E and F show a case wherein a voltagecorresponding to V has a narrow width and a peak value generally equalto V FIGS. 14G and H show the sustaining voltage in the case wherein thestate of the .wall voltage has three stable states, that is, high, low

and zero; further, the waveform of the preparatory converting voltage isable to be the same as that of the sustaining voltage.

As described above, according to this invention, conversion of the stateis carried out in two steps, wherein the preparatory converting voltageand the converting voltage are successively applied, and in thesemiselected cell to which the preparatory converting voltage isapplied; the time when the wall voltage is changed, is shifted but thestate is not converted. In the semi-selected cell to which theconverting voltage is applied, the potential difference between theconverting voltage and the previously applied sustaining voltage is lessthan the firing voltage V and hence the discharge does not take placeand the state is not converted. Accordingly, the semi-select troubledoes not appear at all and the range of the converting voltage, that is,the range of the peak value and pulse width, can be extended. Thepreparatory converting voltage may have the same waveform as thesustaining voltage and the circuit need not be complicated.

Numerous changes may be made in the above described apparatus and thedifferent embodiments of the invention may be made without departingfrom the spirit thereof; therefore, it is intended that all mattercontained in the foregoing description and in the accompanying drawingsshall be interpreted as illustrative and not in a limiting sense.

What we claim is:

1. Apparatus for selectively displaying and storing information, saidapparatus comprising:

a plasma display panel comprising a plurality of energizable radiationemitted elements disposed in an array, each of said emitting elementshaving first and second electrodes defining a discharge regiontherebetween for receiving a discharge gas and wall covering for storingwall charges, said emitting elements having a characteristic firingvoltage;

first means for applying a preparatory converting voltage to the firstelectrode of a selected emitting element of sufficient magnitude toconvert the voltage of the wall charges of the selected emitting cell toa changed voltage; and

second means for applying a converting voltage to the second electrodeof the selected emitting cell of a selected pulse width sufficient tocovert the state of the selected emitting cell from its displaystate toits erase-state, the potential difference between the converting voltageand the changed voltage of the wall charges of the emitting cell beingnot less than the firing voltage of the selected emitting element.

2. Apparatus as claimed in claim 1, wherein there is further includedmeans for applying a sustaining voltage to each emitting element, andwherein said first means provides the preparatory converting voltage ofa waveform substantially similar to that of the sustaining voltage.

3. Apparatus as claimed in claim 2, wherein said first means providesthe converting voltage of a peak value substantially equal to that ofthe sustaining voltage and the pulse width of the converting voltage isnot greater than the pulse width of the symmetric sustaining voltage.

4. A method of selectively energizing a plasma display panel comprisinga plurality of pairs of spaced electrodes for defining a'discharge spacetherebetween filled with a discharge gas, each of the electrode pairshaving a dielectric layer for forming thereon a wall voltage maintainedby periodic sustaining voltage signals applied to the electrodes toeffect a discharge between the electrodes of a pair, whereby the wallvoltage is changed from a first state to a second state, said methodcomprising the steps of;

applying a first voltage signal to the one electrode of a selectedelectrode pair during one cycle of said sustaining voltage signals, saidfirst voltage signal having a potential difference with respect to thesustaining voltage signals and a pulse width of sufficient magnitudes toproduce a discharge to convert the wall voltage; and

thereafter applying a second voltage signal of opposite polarity to saidfirst voltage signal to the other electrode of said selected electrodepair during said one cycle of the sustaining voltage signal, said secondvoltage pulse having a potential difference with respect to theconverted wall voltage produced by said first voltage signal, and apulse width of sufficient magnitudes to produce a discharge to convertthe wall voltage to its second state.

5. The method as claimed in claim 4, wherein the sustaining voltagesignal is symmetric, said first voltage signal is substantially similarin waveform to that of the symmetric sustaining voltage signals, saidsecond voltage pulse having a peak value approximately equal to that ofthe sustaining voltage signals and a pulse width smaller than that ofthe symmetric sustaining voltage signal.

6. The method as claimed in claim 4, wherein the sustaining voltagesignals are non-symmetric and have high and low peak values, said firstvoltage signal is substantially similar in waveform with respect to thatof the non-symmetric sustaining voltage signals of low peak value, andsaid second voltage signal having a peak value intermediate between thehigh and low peak values of the non-symmetric sustaining voltage signalsand a pulse width smaller than that of the non-symmetric sustainingvoltage signals of high peak value.

7. Apparatus for selectively displaying and storing informationcomprising:

a plasma display panel including a plurality of pairs of spacedelectrodes each defining therebetween a discharge space filled with adischarge gas and coated with a dielectric layer for forming thereon awall voltage disposable in first and second states;

first means for applying a periodic sustaining voltage signal to saidelectrode pairs to effect a discharge between said electrodes wherebythe wall voltage is disposed from its first to its second state;

second means for applying a first voltage signal to one electrode of aselected electrode pairs during one cycle of said sustaining voltagesignal, said first voltage signal having a potential difference withrespect to said sustaining voltage signal and a pulse width ofsufficient magnitudes to produce a discharge to convert the wallvoltage; and

third means for applying a second voltage signal of opposite polarity tosaid first voltage signal to the other electrode of said selectedelectrode pair during said one cycle of the sustaining voltage signal,said second voltage signal having a potential difference with respect tothat wall voltage produced by said first voltage signal and a pulsewidth of sufficient magnitudes to effect a discharge to convert the wallvoltage to its second state.

8. Apparatus as claimed in claim 7, wherein said first means provides asymmetric sustaining voltage signal, said first voltage signal beingsubstantially similar in waveform to that of said symmetric sustainingvoltage signal, and said second voltage signal has a peak valueapproximately equal to that of said symmetric sustaining voltage signaland a pulse width smaller than that of said symmetric sustaining voltagesignal.

9. Apparatus as claimed in claim 7, wherein said first

1. Apparatus for selectively displaying and storing information, saidapparatus comprising: a plasma display panel comprising a plurality ofenergizable radiation emitted elements disposed in an array, each ofsaid emitting elements having first and second electrodes defining adischarge region therebetween for receiving a discharge gas and wallcovering for storing wall charges, said emitting elements having acharacteristic firing voltage; first means for applying a preparatoryconverting voltage to the first electrode of a selected emitting elementof sufficient magnitude to convert the voltage of the wall charges ofthe selected emitting cell to a changed voltage; and second means forapplying a converting voltage to the second electrode of the selectedemitting cell of a selected pulse width sufficient to covert the stateof the selected emitting cell from its display-state to its erase-state,the potential difference between the converting voltage and the changedvoltage of the wall charges of the emitting cell being not less than thefiring voltage of the selected emitting element.
 2. Apparatus as claimedin claim 1, wherein there is further included means for applying asustaining voltage to each emitting element, and wherein said firstmeans provides the preparatory converting voltage of a waveformsubstantially similar to that of the sustaining voltage.
 3. Apparatus asclaimed in claim 2, wherein said first means provides the convertingvoltage of a peak value substantially equal to that of the sustainingvoltage and the pulse width of the converting voltage is not greaterthan the pulse width of the symmetric sustaining voltage.
 4. A method ofselectively energizing a plasma display panel comprising a plurality ofpairs of spaced electrodes for defining a discharge space therebetweenfilled with a dischargE gas, each of the electrode pairs having adielectric layer for forming thereon a wall voltage maintained byperiodic sustaining voltage signals applied to the electrodes to effecta discharge between the electrodes of a pair, whereby the wall voltageis changed from a first state to a second state, said method comprisingthe steps of; applying a first voltage signal to the one electrode of aselected electrode pair during one cycle of said sustaining voltagesignals, said first voltage signal having a potential difference withrespect to the sustaining voltage signals and a pulse width ofsufficient magnitudes to produce a discharge to convert the wallvoltage; and thereafter applying a second voltage signal of oppositepolarity to said first voltage signal to the other electrode of saidselected electrode pair during said one cycle of the sustaining voltagesignal, said second voltage pulse having a potential difference withrespect to the converted wall voltage produced by said first voltagesignal, and a pulse width of sufficient magnitudes to produce adischarge to convert the wall voltage to its second state.
 5. The methodas claimed in claim 4, wherein the sustaining voltage signal issymmetric, said first voltage signal is substantially similar inwaveform to that of the symmetric sustaining voltage signals, saidsecond voltage pulse having a peak value approximately equal to that ofthe sustaining voltage signals and a pulse width smaller than that ofthe symmetric sustaining voltage signal.
 6. The method as claimed inclaim 4, wherein the sustaining voltage signals are non-symmetric andhave high and low peak values, said first voltage signal issubstantially similar in waveform with respect to that of thenon-symmetric sustaining voltage signals of low peak value, and saidsecond voltage signal having a peak value intermediate between the highand low peak values of the non-symmetric sustaining voltage signals anda pulse width smaller than that of the non-symmetric sustaining voltagesignals of high peak value.
 7. Apparatus for selectively displaying andstoring information comprising: a plasma display panel including aplurality of pairs of spaced electrodes each defining therebetween adischarge space filled with a discharge gas and coated with a dielectriclayer for forming thereon a wall voltage disposable in first and secondstates; first means for applying a periodic sustaining voltage signal tosaid electrode pairs to effect a discharge between said electrodeswhereby the wall voltage is disposed from its first to its second state;second means for applying a first voltage signal to one electrode of aselected electrode pairs during one cycle of said sustaining voltagesignal, said first voltage signal having a potential difference withrespect to said sustaining voltage signal and a pulse width ofsufficient magnitudes to produce a discharge to convert the wallvoltage; and third means for applying a second voltage signal ofopposite polarity to said first voltage signal to the other electrode ofsaid selected electrode pair during said one cycle of the sustainingvoltage signal, said second voltage signal having a potential differencewith respect to that wall voltage produced by said first voltage signaland a pulse width of sufficient magnitudes to effect a discharge toconvert the wall voltage to its second state.
 8. Apparatus as claimed inclaim 7, wherein said first means provides a symmetric sustainingvoltage signal, said first voltage signal being substantially similar inwaveform to that of said symmetric sustaining voltage signal, and saidsecond voltage signal has a peak value approximately equal to that ofsaid symmetric sustaining voltage signal and a pulse width smaller thanthat of said symmetric sustaining voltage signal.
 9. Apparatus asclaimed in claim 7, wherein said first means provides non-symmetricsustaining voltage signals of high and low peak values, said firstvoltage signal being substantiAlly similar in waveform to that of saidnon-symmetric sustaining voltage of low peak value, and said secondvoltage signal having a peak value intermediate of said high and lowpeak values of said non-symmetric sustaining voltage signals and a pulsewidth smaller than that of said non-symmetric voltage signal of a highpeak value.